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VLSI Implementation and Area Efficient Cordic based Integer DCT Architectures for HEVC

M.Prithivi Raj, G.Suresh Kumar, C.Arunkumar Madhuvappan, S.Selvaraju

In signal progressing domain, recent days there is bottleneck parameter performance like area, latency. To provide area efficient integer Discrete Cosine Transform (DCT) designs for High Efficiency Video Coding (HEVC). So that invoked CORDIC architecture to produce on fly trigonometric output instead of traditional method. In integer DCT have its own style of operation and to calculate twiddle factor of DCT CORDIC architecture actively introduced and make sustainable result in area. The computational complexity has been reduced considerably half as compare to traditional operations. The Experimental result shows that the proposed Dct algorithm has not only reduces the computational complexity. Significantly, it also keeps the better transformation quality of the efficient integer DCT. Therefore, the proposed CORDIC based integer DCT can be used in area efficient and high speed HEVC systems especially in battery-based systems. The design has been verified using Modelsim 6.4se and obtain RTL schematic using Xilinx 13.1 Ise.