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Vedic Multiplier in VLSI for High Speed Applications

G.Ramachandran, T.Muthumanickam, P.M.Murali, Sajith.S.Nair, L.Vasnath

Today most of the processor requires very high speed of operation. Usually DSP processors are based on mathematical approaches. In that multiply-accumulate operation plays vital role. Compared to addition, multiplication process takes large amount of time thus reduces the speed of the processor, consumes some amount of power and area. In this paper we proposed two techniques to improve processor speed based on Vedic mathematics. In Vedic mathematics among 16 sutras, 2 sutras are applicable for multiplication. First method URDHAVA TRIYAKBHYAM sutra which is similar to array multiplication .When number of bits increases, gate delay and area increases slowly compared to other multiplier. So the advanced technique called NIKHILAM sutra is employed. These sutras are meant for faster mental calculation. Though faster when implemented in hardware, it consumes more power than the conventional ones. In this project both the techniques are compared and found that nikhilam is best. This project presents a technique to modify the architecture of the Vedic multiplier by using some existing methods in order increase the processor speed.