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Power Optimization in FPGA through Controller Device

V.Pavithra, T.Suganya, V.Suganya

Field programmable Gate Arrays (FPGAs) are widely used for implementation of digital system design due to their flexibility, low time-to-market, growing density and speed. But the power consumption, especially leakage and dynamic power has become a major concern for semiconductor industries. FPGAs are less power efficient than custom ASICs, due to the overhead required providing programmability. Despite this, power has been largely ignored by the FPGA research community earlier, whose prime focuses on power too. Hence this paper demonstrates some of the most utilized and efficient techniques for power optimization and reduction in FPGAs currently. The Clock gating methodology based on voltage scaling is proposed in this paper. Dual Supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuit. The Coarse Grained Clock network technique is utilized to minimize clock network power in FPGA device.