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IP-SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY ? A LOW POWER DESIGN

D. Harihara Santosh, Lagudu Ramesh Naidu

The growing demand for high density VLSI circuits the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip‟s total power consumption. Motivated by emerging battery-operated application on one hand and shrinking technology of deep sub micron on the other hand, leakage power dissipation is playing a significant role in the total power dissipation as threshold voltage becomes low. Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the VLSI circuits with the performance up to the acceptable level. Here we proposed Novel SRAM architecture called IP-SRAM with separate write sub-cell and read sub-cell. In this paper we designed the total 8 bit SRAM architecture with newly proposed techniques and compare this one with conventional SRAM architecture and we observed that the total power consumption is reduced. Here the total architecture was designed with 180nm technology. These results are compared this with deep submicron technologies.