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Image Analysis and Partitioning For FPGA Implementation of Image Restoration

DR. A. MUTHU KUMARAVEL

It is almost safe to state that there are no applications where images are acquired or processed which do not have active or potential work on image restoration. In the center of work lies an FPGA implementation of an iterative image restoration algorithm. Hardware design for the image restoration algorithm and estimations on the performance of the FPGA implementation is presented. During the restoration of an image each region is restored for as much iteration until the convergence criterion is met. The hardware solution primarily exploits the concept of parallelism in order to gain speed-up against software implementations. Since excessive amount of hardware is needed to restore image of practical size, statistical method for analysis of images is done and hence images are segmented. Results show that the speedup gained for practical systems varies between 6.5 and 10.2 for different images.