A.Bharathi, K.Manikandan , K.Rajasri, P.Santhini
Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carry- look ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To overcome this drawback the domino circuits can be analysed and compared with 65nm technology is used. The proposed work is based on 256 bit Manchester Carry chain(MCC) adders compared with different CMOS technologies.
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