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FPGA Implementation of A Pipelined MIPS Soft Core Processor

Lakshmi S.S, Chandrasekhar N.S

A soft-core processor is a model of hardware description language (HDL) of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. Usually they contain embedded processors that are often in the form of soft-core processors that execute software code. This paper presents a FPGA implementation & verification of a pipelined MIPS 32-bit (microprocessor without interlocked pipeline stages) processor. In this technique soft- core does not requires any reloading or reimplementation of processor after the modification of MIPS code. The design consists of four major blocks: APB, UART, MIPS logic and software tool. The software tool sets the content of the instruction memory space of the processor without having to go through the FPGA implementation process. Soft-core processors are becoming popular solution to support application specific customization. the technique is being demonstrated by writing assembly code for an up/down counter using PERL script. The design architecture is coded using Verilog and realized in Spartan-6 FPGA using Xilinx ISE 14.2.based on the FPGA implementation results, the speed and performance of CPU can be increased