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Efficient VLSI architecture of SISO based Turbo decoder for wireless applications

S.Badrinarayanan, J.M.Mathana, R.Rani Hemamalini

Error correction codes are the essential components of the digital communication and data storage system to ensure robust operation of digital applications wherein turbo code is one of the most attractive near optimal error correction codes. Speed is one of the key factors beside the power consumption and area usage for efficient implementation of turbo decoders. In high speed digital communication such as broadband wireless access based on IEEE 802.16e standard and the fourth generation cellular systems, the design of turbo decoder with high throughput is a critical issue. Since turbo decoders inherently have a long latency and low throughput due to the iterative decoding process. This paper presents VLSI architecture for an efficient soft input soft output based turbo decoder using sliding window method. The speed of operation of the implemented architecture is improved by modifying the value of the branch metrics. The intended SISO based decoder architecture has been implemented using Verilog HDL at RTL level and synthesized to investigate its performance in terms of area usage and timing delay.