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EFFICIENT ENERGY RECOVERY LOGIC: STUDY AND IMPLEMENTATION

Samik Samanta, Rajat Mahapatra, Ashis Kumar Mal

Power consumption is an increasing concern in VLSI circuits. To meet the energy requirements new logic circuits have been developed alternatively to standard CMOS. The so-called adiabatic families reduce energy consumption due to the use of a pulsed power supply. A slowly varying voltage source requires less energy to charge a capacitance if its period is longer than the time constant of the charging path and furthermore, when the supply voltage decreases, the output capacitance is discharged and its stored energy can be recovered by the supply source. The goal of this paper is to compare the performances of various adiabatic families with static CMOS and to investigate their robustness against technological parameter variations. The low power dissipation of adiabatic logic families show their importance in green computing. Here the design and analysis are carried out in HSPICE and Tanner SPICE. We have used 180nm technology.