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DUTY CYCLE CORRECTOR WITH SAR FOR DDR DRAM APPLICATION

M.Ragavan, K.Suganthi

Double Data Rate Dynamic Random Access Memory (DDR DRAM) has become important to develop a low-power high performance DCC(Duty Cycle Corrector) with better duty cycle accuracy. DDR DRAM increases the speed using Successive Approximation Register Duty Cycle Corrector (SAR DCC). The proposed DCC circuit will be implemented in a 0.18- um CMOS process. Here, Adjuster circuit delay line is being modified for low frequency. The main objective of this paper is to achieve fast duty correction . The state-of- the-art DDR DRAM is proposed where a mixed mode DCC. The circuit uses a digital feedback of SAR design process and performance analysis is presented in the paper. The proposed technique will reduce power consumption and speed gets improved in CMOS technology. The entire work can be done by using CADENCE Virtuso