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Design of High Speed Split SAR ADC With Improved Linearity

J.Shaba, S.Pooranachandran

Recently low power Analog to Digital Converters(ADCs) have been developed for many energy constrained applications such as wireless sensor networks and bio-medical applications. Successive approximation register (SAR) ADC are good candidates for low power applications and widely used for low energy application due to its minimum analog blocks. The static linearity performance in terms of the integral nonlinearity and differential nonlinearity and the parasitic effects of the split DAC, are analyzed. A code-randomized calibration technique is done to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulation. Here the SAR ADC is designed in such a way that the control module completely control the splitting up of modules and the speed of operation is changed using low level input bits.A dedicated multiplexer can be used to minimize the capacitor array structure.The control module controls the clock signal and determines the time at which the analog signal should enter the SAR logic.On attaining control over the time of arrival of input signals the speed of conversion can be increased and power utilisation can be minimised.