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Design of FFT Processor Using Modified Modulo 2n+1 Adder

Fathima Nishah P, Ruksana Maitheen

In this paper we present two different architectures for modulo 2n+1 adders and by using this an efficient FFT computation is performed. One of the architecture is based on a sparse carry computation unit in which only some of the carries are computed. In this an inverted circular idempotency property of the parallel prefix carry operator is used and its efficiency is increased by a new prefix operator. The resulting adders will be having less area and power. The second architecture is derived by modifying modulo 2n-1 adders with minor hardware overhead. By using this adders we can implement FFT processor with improved performance