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Design of Controlled Adder /Subtractor Cell Using Shannon Based Full Adder

Sonika Choubey, Rajesh Kumar Paul

This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.