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Design and Implementation of Hybrid SETCMOS 4-to-1 MUX and 2-to-4 Decoder Circuits

N. Basanta Singh

Single Electron Transistor (SET) is an attractive technology for future low power VLSI/ULSI systems. SET has high integration density and ultra-low power consumption. However, Single electron transistors have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. An approach to overcome this problem is to build hybrid circuits of SETs and CMOS. In this work, hybrid SET-CMOS 4-to-1 MUX and 2-to-4 Decoder are designed and implemented. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. All the circuits are verified by means of T-Spice simulation software.