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Design and Implementation of Folded FIR Filter Structures using High Speed Multipliers

P.Premkumar, Dr.S.Kavitha, S.Nandhini

Modern DSP systems are often well suited to VLSI implementation. Indeed, they are often technically feasible or economically viable only if implemented using VLSI technologies.. The paper is focused on the design of an efficient VLSI architecture for FIR filters which aims at reducing the power consumption and also to reduce the hardware complexity. In the existing method, design of folded FIR filter based on conventional multiplier is presented. It does not allow the internal pipelining delays to be exploited. It leads to significant increase in hardware as well as considerable increase in power consumption. It leads to less throughput and increases hardware complexity. In the proposed method, design of folded finite-impulse response (FIR) filters based on pipelined carry-save multiplier is presented . The design is considered at the bit-level and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware complexity. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the conventional multipier . The comparison reveals that the proposed schemes may require 20%–30% less hardware. Due to the lesser carry propagation, the proposed method can achieve low power consumption and higher computational speed strategy.