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Design and Implemenation of High Speed 64- Bit Multiply and Accumulator Unit Using FPGA

Dipika Chauhan, Prof. Kinjal vagadia, Prof. Kirit Patel

In this paper Design of high speed MAC unit based on Vedic multiplier algorithm. Generally MAC useful application such as Digital signal processing like FFT transform , Convolution and correlation. MAC is hardware based module therefore first design of multiplier block and second one is adder block. in this paper to implementation 64bit MAC with reduce the delay and increase the speed of system. The coding done by verilog-HDL and its synthesis and simulation on XILINX ISE.14.5 tool.