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A Novel Architecture of SRAM Cell Using Single Bit-Line

G.Kalaiarasi, V.Indhumaraghathavalli, A.Manoranjitham, P.Narmatha

Low power 6T SRAM cell can be used for different purposes including embedded applications and stand alone applications. Many circuit techniques for active and standby power reduction in static random access memory have been devised. The cell proposed in this paper requires less power and has higher read stability. In existing 8T, 9T and higher transistor count, the read static noise margin is increased but size of the cell and power consumption increases relatively. In the proposed technique the power can be reduced by employing single bit line and by decreasing the switching operational voltage. The SRAM cell operates by charging / discharging of a single bit-line (BL) during read and writes operation, resulting in reduction of dynamic power consumption. All the simulations are done in TANNER EDA software.