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A Modified Bec Logic Design of High Speed Csla For Low Power And Area Efficient Applications

D.Kumaresan, D.Jeyamani M.E, V.Vishnuprasath M.E

Carry Select Adder (CSLA) is one of the fastest efficient adders which are used in many data-processing processors to perform fast arithmetic functions. CSLA is called efficient adder because of less delay and reduced size. Since, area is the major constraint which plays a vital role in integrated circuits. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. The proposed work conveys that it uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular BEC SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular BEC SQRT CSLA. The proposed design has lesser area owing to the modifications in the BEC unit by gate reduction due to combinational logic. The performance factors of the proposed design are evaluated in terms of delay, area, power and their products by simulation tool and implemented in FPGA kit. The results analysis shows that the proposed modified BEC CSLA structure is better than the regular BEC SQRT CSLA.